1. Field of the Invention
The present invention relates to integrated circuit technology. More specifically, the present invention pertains to user-configurable interconnections for array logic and other circuitry.
2. The Prior Art
An integrated circuit uses a network of metal interconnects between the individual semiconductor components which are patterned with standard photolithographic processes during wafer fabrication. Multiple levels of metalized patterns may be used to increase the flexibility of the interconnects. For example in very Large Scale Integration higher density and more complex wiring networks are needed.
It has long been recognized that a user programmable interconnect technique or manufacturer programmability just prior to shipment would allow lower tooling costs and faster delivery time. One technique to accomplish this uses lasers to make or break pre-patterned metal interconnects between an array of logic cells. This is usually performed on the finished wafer prior to assembly or actually in an open package. Another approach uses an array of uncommitted interconnect metal lines using antifuses consisting of an amorphous silicon alloy sandwiched into insulation holes between third and fourth metal layers to provide electrically programmable links.
A gate array circuit is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into the array and the wiring channels and appropriate connections are mask programmed by the integrated circuit gate array vendor to implement the necessary wiring connections that form the circuit function. The gate array vendor then fabricates the circuit according to the constructed masks. Gate arrays are therefore mask programmable and not user programmable.
User-programmable logic arrays are widely used in digital system design in implementing many logic functions and replacing transistor-transistor logic (TTL) parts. Logic arrays currently available include PLA (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), EPLDs (Erasable Programmable Logic Devices) and logic cell arrays using RAM (Random Access Memory) cells to define logic cell function and interconnect configuration. Programmable logic circuit arrays have been usually implemented in bipolar technology using fusible links which, when programmed, define the logic function to be implemented. An example of such a link is the polysilicon fuse which is programmed" when it is blown and prevents current flow in a circuit. Such fusible links often require large current to operate and require extra area on the integrated circuit. More recently, electrically programmable read-only memory (EPROM) and electrically erasable read-only memory (EEROM) technology has been used to construct programmable logic circuit arrays. In the latter case, EPROM or EEROM cells are programmed and the stored values used to define circuit configuration.
Existing programmable array logic circuits use an AND plane of gates followed by an OR plane of gates to implement a particular logic function. The AND plane is usually user programmable while the OR plans programming is usually fixed. Variations to this architecture include registered outputs of the OR plane, partitioning of the array into smaller AND-OR arrays or macrocells and programmable input/output (I/O) architecture to implement several options of I/O requirements. The RAM implemented logic cell array consists of a matrix of configurable blocks which are programmed to implement a particular logic function by loading an internal RAM with the appropriate data pattern. The array has a network of user-programmable MOS transistors acting as electrical switches as well as vertical and horizontal lines or wires to connect the logic blocks together and to the I/O blocks.
Existing user-programmable array logic circuits described above are useful in implementing certain logic functions but have several disadvantages. First, the use of an AND plane/OR plane combination of gates to implement logic functions is inflexible and is not well suited to the requirements of random logic functions. Second, the utilization factor of such an array is quite low and a large number of gates are wasted. Third, the integrated circuit chip area-per-functional capability is usually quite high.
Gate arrays, on the other hand, are more flexible than programmable array logic and much more efficient in their gate utilization and integrated circuit chip area utilization. However, their main disadvantage is that they are mask programmable and not user programmable. This results in much higher costs to develop the circuit and its unique mask pattern, and a long turn-around time to order and receive integrated circuit chips.